Yijun Cui, Yang Chen, Bei Wang, Ziying Ni, Lixia Han, Fei Lyu, Chenghua Wang, Weiqiang Liu

DRR-NTT: Efficient NTT Accelerator in Lattice-Based Cryptography By Dimensionality Reduction in RRAM

Introduction

Drr-ntt: efficient ntt accelerator in lattice-based cryptography by dimensionality reduction in rram. DRR-NTT presents an RRAM-based NTT accelerator for Lattice-Based Cryptography. Enhance PQC & FHE with reduced latency, high precision (10^-6), and superior energy efficiency.

Abstract

Lattice-based cryptographic (LBC) algorithms, including Post-Quantum Cryptography (PQC) schemes and Fully Homomorphic Encryption (FHE), represent one of the most important families of quantum-resistant cryptosystems. A key computational primitive shared across these lattice-based algorithms is the Number Theoretic Transform (NTT), which often constitutes a performance bottleneck in practical implementations. Resistive random access memory (RRAM) is particularly well-suited for compute-in-memory (CIM) architectures due to its non-volatility, high density, analog computing capability, and inherent parallelism. Nevertheless, achieving high computational accuracy for NTT operations within RRAM-based CIM architectures remains a significant challenge for the efficient deployment of LBC.In this paper, we propose a novel NTT accelerator based on RRAM array, which is called DRR-NTT. First, we utilize a matrix decomposition method to create the most compact RRAM-CIM-based NTT architecture to date, which reduces system latency and significantly mitigates inter-column interference in the RRAM array. Second, we use a 3-bit weight mapping scheme for RRAM-based NTT accelerators, optimizing array utilization and accommodating various modulus values. Unlike prior works that relied solely on simulations, we incorporate real-world resistance measurements from fabricated RRAM devices into our quantization error analysis. Under equivalent conditions, our architecture achieves error control at the 10−6 level, surpassing previous CIM-based designs by over three orders of magnitude. Furthermore, we are the first to introduce the Plantard modular multiplication algorithm into RRAMbased CIM architectures, enhancing it to align with RRAM characteristics. This improvement boosts the efficiency of modular reduction operations while minimizing the hardware complexity and power consumption typically associated with managing precomputed twiddle factor matrices.Our architecture fully leverages the parallel nature of RRAM arrays and meets the high precision requirements of cryptography; it not only enhances throughput but also minimizes data movement overhead, leading to improved energy efficiency. Experimental results demonstrate that our proposed accelerator achieves a latency reduction of 1.5x ∼ 2.47x, an improvement in throughput and energy efficiency ranging from 1.6x ∼ 4.52x and over 1.5x improvement in throughput/area compared to state-of-the-art CIM-based solutions. This research will provide technical support for the efficient and high-precision implementation of LBC on RRAM.

Review

This paper introduces DRR-NTT, a novel RRAM-based compute-in-memory (CIM) accelerator designed to address the performance bottlenecks of Number Theoretic Transform (NTT) operations in Lattice-based Cryptography (LBC), including Post-Quantum Cryptography (PQC) and Fully Homomorphic Encryption (FHE). While RRAM-based CIM architectures offer significant potential for parallel and energy-efficient computation due to their inherent characteristics, achieving the high computational accuracy required for cryptographic NTT operations remains a substantial challenge. The authors effectively set the stage by highlighting the critical role of NTT in LBC and the specific hurdles faced when attempting to implement these demanding computations within RRAM arrays. The core of DRR-NTT lies in several key innovations. First, the authors propose a matrix decomposition method that yields the most compact RRAM-CIM-based NTT architecture to date, significantly reducing system latency and mitigating inter-column interference. Second, a 3-bit weight mapping scheme is introduced, optimizing array utilization and accommodating diverse modulus values. Crucially, the paper distinguishes itself by incorporating real-world resistance measurements from fabricated RRAM devices into its quantization error analysis, demonstrating an impressive error control at the 10⁻⁶ level – an improvement of over three orders of magnitude compared to prior CIM-based designs. Furthermore, the work is pioneering in its integration and enhancement of the Plantard modular multiplication algorithm for RRAM-based CIM, tailored to RRAM characteristics, which improves modular reduction efficiency while minimizing hardware complexity and power. The experimental results validate the efficacy of the proposed DRR-NTT accelerator. It achieves substantial performance gains, including a latency reduction of 1.5x to 2.47x, an improvement in throughput and energy efficiency ranging from 1.6x to 4.52x, and over a 1.5x enhancement in throughput/area compared to state-of-the-art CIM-based solutions. By fully leveraging the parallel nature of RRAM arrays and successfully meeting the stringent precision requirements of cryptography, DRR-NTT not only boosts throughput but also minimizes data movement overhead, leading to improved energy efficiency. This research provides a robust technical foundation for the efficient and high-precision implementation of LBC schemes on RRAM platforms, offering a significant step forward in the practical deployment of quantum-resistant cryptographic systems.

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